The present invention relates to wireless communications, and specifically to wireless communications where voltage controlled oscillator (VCO) gain tracking is used for setting modulation gain.
Phase locked loops (PLLs) are used to drive local oscillators for upconverters (transmitters) and downconverters (receivers) in telecommunications equipment and systems. PLLs can also be equipped with modulators and/or demodulators for the associated transmitters and receivers of the type that respectively send and receive constant envelope signals such as signals having phase and/or frequency modulation, as well as with non-constant envelope transmitters and receivers in which a signal is expressed as a combination of multiple constant envelope signals (linc modulation) or as a constant envelope signal and a separate envelope-defining signal (polar modulation).
The accuracy of PLL based modulators and demodulators depends on whether the PLL bandwidth is sufficiently large compared to the bandwidth of the signals being transmitted and received. However, the PLL bandwidth may be limited by the need for low output radio frequency (RF) spectrum noise at offset frequencies near the edge of the modulation bandwidth. For many signal types, the signal bandwidth is typically near channel spacing, and low spectral noise is needed so that blocking effects from signals on adjacent channels can be minimized.
Dual port PLLs are commonly used for broadening the PLL response to a modulation or demodulation signal while at the same time maintaining low output RF spectrum noise. In, for example, a fractional-N modulating synthesizer, there are two signal paths between the data input, and the phase or frequency modulated output signals. Signal flow analysis requires that networks containing a single loop and having more than one forward path have a transfer function determined by the sum of the transfer functions of the forward paths divided by one plus the transfer function of the loop.
However, modulation accuracy is highly dependent on variations in Kv, the VCO gain. The degree of sensitivity to variation in Kv depends on the PLL bandwidth. For lower PLL bandwidths, the sensitivity of modulation accuracy to Kv variation may become higher than can be tolerated by system requirements.
For example, in a GMSK fractional-N modulator, the signal bandwidth is approximately 200 KHz, and there are strict spectral noise requirements at the 400 KHz offset frequency of xe2x88x92113 dBC/Hz. In commercially available PLL integrated circuits the noise stimulus from the phase detector output dominates the output RF spectrum. A typical in-band noise level is approximately xe2x88x92100 dBC/Hz. A 150 KHz PLL can be employed resulting in nominal 15 dB rejection to the phase detector noise stimulus at 400 KHz. This results in an output RF spectrum noise of xe2x88x92114 dBc/Hz, which marginally passes the requirement. However the PLL rejection is insufficient when PLL parameters vary in such a way as to widen the PLL bandwidth. Therefore, there is a need for lower PLL bandwidth in order to obtain additional margin in the output RF spectrum noise. Adjusting the loop filter transfer function can reduce the PLL bandwidth. For instance, in order to reduce the bandwidth by a factor of 0.5 and bring the PLL bandwidth down to 75 kHz, loop filter resistors can be reduced by a factor of 2 and the capacitors increased by a factor of 4.
However, if the PLL bandwidth is lowered as discussed above, modulation distortion becomes problematic due to variations in Kv. For example, in GSM system modulation, distortion is defined as global phase error, which is a spectrally weighted function of the rms phase error over the modulation bandwidth. Global phase error caused by PLL distortion is primarily a function of variation in Kv from the ideal value of the inverse of the high port gain. Conversely, the global phase error can be said to be a function of the variation in the high port gain from the ideal value of 1/Kv. Hardware stabilization or control of Kv is difficult, but the variable high port gain can be controlled quite easily by programming a multiplying DAC. For the two PLL bandwidth cases discussed above, in the 150 KHz case global phase error has been shown to be less than 5xc2x0 for an approximate 2:1 variation of the gain setting. Therefore, with a fixed gain setting, the PLL is tolerant of an approximately 2:1 variation in Kv. However, in the 75 KHz case, the PLL has been shown to be approximately three times more sensitive to variations in Kv, whereas tolerances of Kv of less than 1.5:1 can be difficult and expensive to realize with available oscillators.
Therefore, what is needed is a method and system for optimally adjusting the high port gain of a dual port PLL in a synthesizer based on the value of Kv.